1. Field of the Invention
The present invention relates to a voltage converter, and more particularly, to a DC/DC voltage converter capable of minimizing the voltage spike efficiently by utilizing a protection circuit.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram of an example of a prior art flyback DC/DC voltage converter 100. As shown in FIG. 1, the voltage converter 100 comprises an electronic induction device 105, a switch device 110, a control circuit 115, and an over-current detection circuit 120. The electronic induction device 105 has a diode D, a first electronic induction circuit L1, and a second electronic induction circuit L2, wherein the diode D acts as a rectifier to allow one-way current flow, and the first electronic induction circuit L1 and second electronic induction circuit L2 are implemented by coupling inductors or transformer and utilized for converting an input voltage signal Vin into an output voltage signal Vout. The switch device 110 comprises a transistor Q1 that will be selectively turned on/off by a first control signal Sc1 generated from the control circuit 115. The control circuit 115 comprises a plurality of resistors R1, R2 serving as a feedback path, an error amplifier OP1, a PWM control loop 125, and a driver 130. The feedback voltage
      V    fb    ⁡      (                  V        fb            =                        V          out                ×                              R            2                                              R              1                        +                          R              2                                            )  is compared with a reference voltage Vref1 by the error amplifier OP1, and then the resultant output is fed into the following PWM control loop 125. The driver 130 drives the transistor Q1 using a control signal Sc1. The PWM control loop 125 references the output from the error amplifier OP1 for adjusting the duty cycle of the transistor Q1 and then making the output voltage signal Vout stabilized at a target level. Further description is well known to those skilled in the art and is therefore not detailed here for brevity. Additionally, the over-current detection circuit 120 comprises an over-current detection device 135, a comparator OP2, and a leading edge blanking device 140. The over-current detection circuit 120 is utilized for performing an over-current detection and outputting an indication signal S1 when detecting that a current I1 passing through the switch device 110 exceeds a predetermined current limit.
Please refer to FIG. 2. FIG. 2 is a waveform diagram illustrating the operation of the prior art flyback DC/DC voltage converter 100 shown in FIG. 1. As shown in FIG. 2, from the voltage converter 100's start time to time T1, the transistor Q1 is turned on and the energy brought by the input voltage signal Vin will be stored at the first electronic induction circuit L1. It should be noted that no energy coupling is established between these two electronic induction circuits (coupling inductors or transformer) L1 and L2 due to the reverse biased diode D. Once the transistor Q1 is turned off, i.e. from time T1 to time T2, the energy stored at the first electronic induction circuit L1 will be transferred/coupled into the second electronic induction circuit L2 to output the output voltage signal Vout because the diode D is forward biased by the polarity change of the second electronic induction circuit L2 as the first electronic induction circuit L1 changes its polarity. Since the electronic induction device 105 is not ideal, the voltage level at the node N1 (i.e. VN1) will have a voltage spike Vspike caused by a leakage inductance of the first electronic induction circuit L1, parasitic capacitance of the first electronic induction circuit L1, and output capacitance of the transistor Q1. An equation related to the voltage level at the node N1 (i.e. VN1) is shown below:
                                          V                          N              ⁢                                                          ⁢              1                                =                                                    V                spike                            +                              V                                  i                  ⁢                                                                          ⁢                  n                                            +                                                V                  out                                N                                      =                                                            I                  1                                ×                                                                            L                      leak                                                                                      C                        p                                            +                                              C                        oss                                                                                                        +                              V                                  i                  ⁢                                                                          ⁢                  n                                            +                                                V                  out                                N                                                    ,                            Equation        ⁢                                  ⁢                  (          1          )                    
wherein N represents a turns ratio of the electronic induction device 105, Lleak represents the leakage inductance of the first electronic induction circuit L1, Cp represents the parasitic capacitance of the first electronic induction circuit L1, and Coss represents an output capacitance of the transistor Q1. Assuming that a voltage level of the input voltage signal Vin is equal to 3 volts, a voltage level of the output voltage signal Vout is designed to provide 24 volts, and the turns ratio N is equal to 8. Equation (1) can be rewritten as below:
                                          V                          N              ⁢                                                          ⁢              1                                =                                                    V                spike                            +              3              +                              24                8                                      =                                          V                spike                            +              6                                      ,                            Equation        ⁢                                  ⁢                  (          2          )                    
In order to prevent the transistor Q1 from breakdown, the voltage level VN1 must be smaller than the maximum sustainable voltage difference of the transistor Q1. In this example, if the maximum sustainable voltage difference across the transistor Q1 is limited to 20 volts, the voltage spike Vspike needs to be smaller than 14 volts; otherwise, the transistor Q1 will be damaged.
In addition, the comparator OP2 compares the voltage difference across the switch device 110 caused by the current I1 and a reference voltage Vref2 to determine if the current I1 is larger than a predetermined current limit value. Usually, the predetermined current limit value is set to be smaller than the maximum continuous sustainable current passing through the transistor Q1. For example, if the reference voltage Vref2 is equal to 0.8 volts, the impedance of the switch device 110 is equal to 200 micro Ohm, the comparator OP2 will notify the over-current detection device 135 to switch off the transistor Q1 through the control circuit 115 when the voltage difference across the switch device 110 is larger than 0.8 volts (i.e. the current I1 is larger than 4 A). Furthermore, as shown in FIG. 2, when the transistor Q1 is turned on, the current I1 will have large current swing such that the leading edge blanking device 140 is needed to prevent the over-current detection device 135 from false triggered. Usually, the leading edge blanking device 140 built in a leading edge blanking time (probably 300˜500 nanoseconds). In the leading edge blanking time, the over-current detection device 135 is disabled.
However, when the voltage converter 100 is operated under an abnormal operating condition, for example, when the first electronic induction circuit L1 is shorted by a short line (note: the short line has small parasitic inductance) and then the converter 100 is enabled, the current I1 will rise very fast and the value will be very high in the leading edge blanking time. In theory the current I1 could be up to 15 A, this is estimated by the voltage level of the input voltage signal Vin (i.e. 3 volts) divided by the impedance of the switch device 110 (i.e. 0.2 Ohm) is equal to 15 A. After the leading edge blanking time is finished, the over-current detection device 135 is started and then the transistor Q1 is turned off such that the energy stored at the short line will transfer to the voltage spike across the transistor Q1, which increases the voltage level at the node N1 (i.e. VN1) and this voltage level VN1 will be much larger than the voltage level VN1 under the normal operating condition. Assuming that the short line has 4 nH parasitic inductance, the output capacitance of the transistor Q1 (i.e. Coss) is 200 pF, and the current I1 is up to 8 A in the leading edge blanking time. From Equation (1), the voltage spike under this abnormal operating condition may be larger than 35 volts. Therefore, the transistor Q1 will be damaged since the voltage spike is larger than the maximum sustainable voltage difference of the transistor Q1.
There are two conventional schemes provided for solving the problem caused by the voltage spike under the abnormal condition. The first scheme is to provide a snubber circuit having a resistor and a capacitor in series, and to connect the snubber circuit between the node N1 and ground. The snubber circuit is utilized for preventing the voltage level at the node N1 (i.e. VN1) from raising very much immediately such that the effect caused by the voltage spike can be alleviated. However, the capacitor is with several nano Faraday, and the resistor is with several Ohm, thus the scheme will increase cost, PCB board space and decrease the total power conversation efficiency of the voltage converter 100. This is a drawback for applying the voltage converter 100 to mobile products.
Another scheme is to lower the sink driver capacity of the transistor Q1 such that the turn off period of the transistor Q1 becomes longer. The effect caused by the voltage spike can be reduced since the impedance of the transistor Q1 can be used to consume the energy, introduced by the voltage spike during the Q1 turn off period. However, under the normal operating condition, the switching loss is also increased and the power conversion efficiency of the voltage converter 100 is then decreased. Moreover, the switching loss will become more serious for portable products, because portable products usually operate in high switching frequency.